• Register Summary
  • DDRB - Port B Data Direction Register
  • PORTB - Port B Data Register
• Timers
  • TCCR0A - Timer 0 Counter Control Register A
  • TCCR0B - Timer 0 Counter Control Register B
  • TCNT0 - Timer 0 Counter Register
  • 0CR0A - Timer 0 Output Compare Register A
  • 0CR0B - Timer 0 Output Compare Register B
  • TCCR1 - Timer 1 Counter Control Register
  • TIMSK - Timer 0 Interrupt Mask Register
    • Wave Form Generation
  • TCCR1 - Timer 1 Counter Control Register
  • Timer modes
    • Normal
    • CTC - Clear Timer to Compare Match
    • Fast PWM
    • Waveform Generation
• Interrupts
  • TIMSK - Timer Interrupt Mask Register
  • Hardware interrupts
    • External interrupts
    • Pin change interrupt
  • Timer interrupts
• ADC
  • ADMUX - ADC Multiplexer Select
  • ADCSRA - ADC Control and Status
  • ADCSRB - ADC Control and Status
  • Manual Triggering
  • Auto triggering

Register Summary

DDRB - Port B Data Direction Register

PORTB - Port B Data Register

Timers

TCCR0A - Timer 0 Counter Control Register A

COM0A[1:0] - control behavior on OC0A compare match

COM0B[1:0] - control behavior on OC0B compare match

WGM0[2:0] - control bits for waveform generation mode. WGM02 is in TCCR0B

TCCR0B - Timer 0 Counter Control Register B

FOC0A -

FOC0B -

WGM02 - part of waveform generation settings, see TCCR0A

CS0[2:0] - set Timer 0 prescaler

TCNT0 - Timer 0 Counter Register

Contains current counter value for Timer 0

0CR0A - Timer 0 Output Compare Register A

Compared against Timer 0 counter value to trigger some event, like an output compare interupt

0CR0B - Timer 0 Output Compare Register B

Compared against Timer 0 counter value to trigger some event, like an output compare interupt

TCCR1 - Timer 1 Counter Control Register

CTC1 - clear Timer 1 after compare match with OCR1C

PWM1A - enable PWM mode for OCR1A, (counter reset after compare match with OCR1C)

COM1A[1:0] - control OC1A behavior on compare match with OCR1A

CS1[3:0] - set Timer 1 prescaler

TIMSK - Timer 0 Interrupt Mask Register

Wave Form Generation

TCNT0 - counter

OCR0A - stationary threshold

OC0A - output from compare

OCR0B - stationary threshold

OC0B - output from compare

TCCR1 - Timer 1 Counter Control Register

CTC1 - clear TCNT1 on compare match with OCR1C

PWM1A - enable PWM mode using OCR1A, reset on compare match with OCR1C

COM1A1/COM1A0 - determine output behavior of OC1A on compare match with OCR1A

TCNT1 - counter

Timer modes

BOTTOM - always 0

MAX - size of the counter

TOP - can be either MAX or OCRxx, depending on mode

Normal

Timer counts up to TOP=0xFF then overflows and resets. Use OCRxx to either toggle output (OCxx) or trigger an interrupt

CTC - Clear Timer to Compare Match

Timer is cleared when TCNT* (timer count) passes 0CR* (output compare)

Fast PWM

Timer counts up to TOP then resets to BOTTOM.

Waveform Generation

Interrupts

sei() - enable interrupts

TIMSK - Timer Interrupt Mask Register

0CIE1A - call TIMER1\_COMPA\_vect compare match

0CIE1B - call TIMER1\_COMPB\_vect compare match

0CIE0A - call TIMER0\_COMPA\_vect compare match

0CIE0B - call TIMER0\_COMPB\_vect compare match

TOIE1 - call TIMER1\_OVF\_vect on timer overflow

TOIE0 - call TIMER0\_OVF\_vect on timer overflow

Hardware interrupts

External interrupts

Only available to certain pins (only INT0 on attiny85) Interrupts must be unmasked (enabled)

GIMSK - set INT0 to enable interrupt

MCUCR - set ISC01/ISC00 to interrupt on change/rising/falling edge

#include <avr/io.h>
#include <avr/interrupt.h>

int main(void)
{
  DDRB |= 1 << PB1;             // enable output on PB1

  GIMSK = 1<<INT0;              // unmask INT0 external interrupt
  MCUCR = 0<<ISC01 | 1<<ISC00;  // enable interrupt on rise/fall

  sei();                        // global interrupt enable

  while(1) {}
}

// interrupt service routine (ISR) for timer 0 A compare match
ISR(INT0_vect)
{
  PORTB ^= (1<<PB1);
}

Pin change interrupt

These are still technically 'external' to the chip. Only one interrupt per port, but any pin on the port can trigger it. Interrupts must be unmasked (enabled)

GIMSK - set PCIE to unmask all PCI on port (only 1 port on attiny85)

PCMSK - set PCINTx to enable PCI on PCINT0 pin

#include <avr/io.h>
#include <avr/interrupt.h>

int main(void)
{
  DDRB = 1 << PB1;  // enable output on PB1

  GIMSK = 1<<PCIE;   // turn on pin change interrupts
  PCMSK = 1<<PCINT0; // unmask PCINT0 pin change interrupt

  sei();             // global interrupt enable

  while(1) {}
}

// interrupt service routine for PCINT0
ISR(PCINT0_vect)
{
  PORTB ^= (1<<PB1);
}

Timer interrupts

TIMSK - timer interrupt mask

TIMER1\_COMPA\_vect - call on compare match with OCR1A

TIMER1\_COMPB\_vect - call on compare match with OCR1B

TIMER1\_OVF\_vect - call when TOP is reached

#include <avr/io.h>
#include <avr/interrupt.h>

void main() {
    DDRB = (1<<PB1);  // set PB1 to output

    // enable timer clock and set prescaler to 1
    TCCR1 =  1<<CS10;

    // run TIMER1_COMPA interrupt when there's a match on timer 1, comparator A
    TIMSK |= 1<<OCIE1A;

    OCR1A = 255; // TOP - when to toggle OC1A
    OCR1C = 255; // when to reset TCINT1

    sei(); //enable interrupts

    while(1){}
}

ISR(TIMER1_COMPA_vect){
    PORTB ^= 1<<PB1; // toggle output
}

ADC

ADMUX - ADC Multiplexer Select

REFS[2:0] - used to set voltage reference for ADC

ADLAR - enable left adjust for result (ADH contains 8 MSBs of ADC reading)

MUX[3:0] - set adc to use

ADCSRA - ADC Control and Status

ADEN - enable ADC

ADSC - enable a single measurement in manual mode, or enable auto mode

ADATE - enable ADC auto triggering

ADIF - this output is set when the ADC measurement is ready. cleared automatically if ADC interrupt is used

ADIE - enable ADC interrupt ADC_vect

ADPS[2:0] - adc prescaler

ADCSRB - ADC Control and Status

BIN - enables bipolar mode. 9 bit resolution + sign bit

IPR - reverse polarity in bipolar mode

ADTS - control ADC triggering in auto mode

Manual Triggering

Auto triggering

ADATE - ADC auto trigger enable